ASIC Verification Engineer

Job Title

ASIC Verification Engineer

Role Summary

Individual contributor responsible for verification of ARM-related IP blocks (CPU Cortex-A v9, GPU Mali, Debug CSS600/CoreSight) within ASIC projects. Focus is on designing and executing verification plans, developing UVM/SystemVerilog testbenches, coverage analysis, and debugging to ensure delivery quality.

Experience Level

Mid-level — expects proven experience (typical: 5+ years) in ASIC verification and modern verification methodologies.

Responsibilities

Primary responsibilities include ownership of block-level verification and collaboration with cross-functional teams to ensure design quality.

• Develop and execute verification plans for ARM-related IP blocks (CPU, GPU, Debug).
• Design and implement UVM/SystemVerilog test environments and C-based test cases for IP configuration and validation.
• Create constrained-random tests, assertions, and perform coverage-driven verification and coverage analysis.
• Run and analyze gate-level simulation (GLS) and assist with timing- and integration-related verification tasks.
• Debug RTL, test failures, and collaborate with design teams to resolve issues.
• Maintain and reuse vendor/manufacturer test benches and verification assets at block and subsystem levels.
• Contribute to process improvements and verification methodology initiatives across the global verification team.

Requirements

Must-have technical skills and experience are listed first; additional desirable skills follow.

• Must-have: 5+ years of hands-on ASIC verification experience using UVM/SystemVerilog.
• Must-have: Experience with constrained-random verification, assertions, coverage metrics and coverage analysis.
• Must-have: Gate-level simulation experience and familiarity with verification KPIs.
• Must-have: Strong practical knowledge of ARM-related IPs (Cortex-A v9, Mali, CSS600/CoreSight).
• Must-have: Ability to design and implement C-based test cases and reuse manufacturer-provided test benches.
• Nice-to-have: Experience building UVM-based environments for block and subsystem verification.
• Nice-to-have: Ability to read and understand RTL (SystemVerilog, Verilog, VHDL).
• Nice-to-have: Experience with revision control systems, CI/CD for verification flows.
• Nice-to-have: Strong communication, documentation, and cross-team collaboration skills.

Education Requirements

Not specified.

About the Company

Company: Capgemini

Headquarters: Paris, France

Global consulting, technology and engineering services firm offering digital and business transformation, cloud, AI, and engineering/R&D services across industries. Employs around 340,000 people in 50+ countries and provides end-to-end solutions from strategy and design to engineering.