ASIC Verification Engineer
CapgeminiJob Title
ASIC Verification Engineer
Role Summary
Individual contributor responsible for verification of ASIC/SoC blocks with a strong focus on ARM-related IPs (CPU Cortex-A v9, GPU Mali, Debug CSS600/CoreSight). Role covers the full verification lifecycle: specification review, plan creation, test development, environment implementation, coverage analysis and debug. This position is remote.
Experience Level
Mid-level. The posting requests proven hands-on verification experience; ~5+ years of relevant industry experience is preferred.
Responsibilities
The following are the primary responsibilities for this role:
- Define and execute verification plans for core IP blocks (ARM CPUs, GPUs, debug subsystems).
- Develop UVM/SystemVerilog test environments and C-based test cases to configure and exercise ARM IPs.
- Perform coverage-driven verification, coverage analysis and reporting; define and track verification metrics.
- Debug RTL and system issues across simulation and gate‑level simulation environments.
- Conduct architectural and design reviews; provide verification feedback to improve requirements/specifications.
- Collaborate with global verification and design teams to share findings and improve verification methodologies and processes.
- Own verification deliverables through the full project lifecycle, including reuse of vendor test benches where applicable.
Requirements
Must-have skills and experience:
- 5+ years of hands-on ASIC/SoC verification experience with industry-standard methodologies.
- Practical experience with UVM and SystemVerilog-based verification environments.
- Experience with formal verification, constraint-random verification, assertions, and coverage-driven verification.
- Gate-level simulation experience and ability to perform coverage analysis and debug across RTL and GLS.
- Strong understanding and hands-on experience with ARM-related IPs (CPU Cortex-A v9, GPU Mali, Debug CSS600/CoreSight).
- Experience writing C-based test cases to configure and test ARM IPs and reusing manufacturer-provided test benches.
Nice-to-have:
- Experience creating reusable UVM test environments for block and subsystem verification.
- Ability to read and interpret RTL (SystemVerilog, Verilog, VHDL).
- Familiarity with revision control systems and CI/CD for verification flows.
- Strong communication, documentation and cross-team collaboration skills.
Education Requirements
Not specified.
About the Company
Company: Capgemini
Headquarters: Paris, France
Global consulting, technology and engineering services firm offering digital and business transformation, cloud, AI, and engineering/R&D services across industries. Employs around 340,000 people in 50+ countries and provides end-to-end solutions from strategy and design to engineering.
