ASIC/SoC RTL Design Engineer

Job Title

ASIC/SoC RTL Design Engineer

Role Summary

Contract RTL design engineer to develop and integrate SoC components across architecture, RTL, and verification on a 6+ month onsite engagement in the San Jose/Santa Clara area. In-person interview required.

Work focuses on SoC RTL development, integration of processors and I/O IP, and collaboration with design, verification, and bring-up teams.

Experience Level

Mid-level (specific years of experience not stated).

Responsibilities

Primary responsibilities include:

• Design and implement RTL for SoC components.
• Perform verification, simulation, and debugging of RTL.
• Support synthesis flows and timing-closure activities.
• Integrate and validate ARM cores, DDR, PCIe, Ethernet, and other IP.
• Collaborate with design, verification, and bring-up teams to resolve integration and silicon issues.

Requirements

Must-have skills and attributes:

• Proven experience in ASIC/SoC design and RTL coding.
• Familiarity with ARM cores and standard I/O interfaces (e.g., DDR, PCIe, Ethernet).
• Available to work 100% onsite in the San Jose/Santa Clara, CA area; in-person interview required.
• Available as a contractor for a 6+ month engagement.

Nice-to-have:

• Experience with synthesis, timing closure, and bring-up support.

Education Requirements

Not specified.

About the Company

Company: Dexian

Talent and technology staffing firm offering global workforce and technology solutions. Dexian provides recruitment, staffing, and professional services with over 70 locations and a 10,000+ member team, focusing on tech placements and minority-owned business leadership.