Role Summary
Join AMD's Silicon Design team as a Senior ASIC Design Engineer, responsible for designing and developing cutting-edge IPs for next-generation embedded products. You will manage the complete RTL design lifecycle, from micro-architecture specification to production silicon, working on complex IP designs.
Experience Level
This position requires advanced experience in ASIC design, with a proven track record of at least 2 production tape-outs. Strong ownership and the ability to mentor junior engineers are essential.
Responsibilities
- Author detailed micro-architecture specifications and own the Verilog RTL implementation of major IP blocks, ensuring compliance with Performance, Power, and Area (PPA) targets.
- Drive the design process from concept through production silicon, including all phases: specification, RTL coding, lint checks, synthesis, timing analysis, verification, and validation.
- Develop timing constraints and perform static timing analysis, collaborating with physical design teams to achieve timing closure.
- Integrate ASIC IP blocks into full-chip SoC environments, ensuring proper connectivity and protocol compliance.
- Collaborate with verification teams to ensure functional coverage and implement design-for-test features.
- Work with physical design engineers on aspects like floor planning and power grid design.
- Automate tasks and improve design quality using scripting languages such as Python and Perl.
- Engage with cross-functional teams to resolve technical challenges and deliver high-quality silicon on schedule.
Requirements
The ideal candidate will possess expert-level Verilog RTL coding skills and a deep understanding of the ASIC design process, including knowledge of tape-out, timing constraints, and SoC integration. Proven experience with on-chip interconnect protocols and strong scripting abilities are also crucial.
Education Requirements
A Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is required.