ASIC/SoC Design Engineer, RTL Design

Role Summary

The ASIC/SoC Design Engineer will be an integral part of AMD's Silicon Design team, responsible for the design and development of advanced IPs for embedded products. This role encompasses ownership of the complete RTL design lifecycle, from micro-architecture specifications to production silicon, focusing on complex IP designs.

Experience Level

We are looking for a senior candidate with extensive experience in ASIC/SoC design, specifically tailored towards those who have a strong command of RTL design processes and have successfully overseen multiple production tape-outs.

Responsibilities

• Author detailed micro-architecture specifications and manage the Verilog RTL implementation of major IP blocks, ensuring adherence to PPA (Performance, Power, Area) targets and timing constraints.
• Lead the entire ASIC development lifecycle through all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, and beyond to physical design integration and post-silicon validation.
• Develop timing constraints (SDC), perform static timing analyses (STA) using industry-standard tools, and work with physical design to ensure timing closure.
• Integrate complex ASIC IP blocks into full-chip SOC environments while maintaining compliance with connectivity and interface protocols.
• Collaborate with verification teams to ensure design functionality, implement DFT and DFD features, and participate in design quality reviews.
• Work closely with physical design engineers on floor planning and power grid design to ensure manufacturing readiness.
• Create automation scripts using Python, Perl, or Tcl to improve design quality and workflow efficiency.
• Collaborate with cross-functional teams to address technical challenges and ensure timely delivery of high-quality silicon.

Requirements

Applicants should have a proven track record with at least 2 production ASIC tape-outs in senior roles, along with expertise in Verilog RTL coding and a comprehensive understanding of the ASIC design flow. Candidates should also have experience with SDC timing constraints and integrating complex IP blocks into SOC designs.

Education Requirements

A Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is required for this position.