ASIC/RTL Design Engineer II
TekWissenJob Title
ASIC/RTL Design Engineer II
Role Summary
12-month onsite ASIC/RTL design role based in San Jose, CA focused on digital SoC design and RTL implementation for advanced CMOS processes. The engineer will work with ARM cores and a range of IP (Ethernet, DDR, DMA, PCIe, SATA) and coordinate with architecture, physical implementation, software, and silicon bring-up teams.
Experience Level
Mid-level (Engineer II). Years of experience not specified.
Responsibilities
Accountable for RTL delivery, verification, and integration across the SoC design cycle.
- Define chip features and develop micro-architectural specifications.
- Convert micro-architectural specs into RTL and synthesizable logic.
- Perform RTL verification, emulation, debug, synthesis, and timing closure.
- Integrate and validate ARM cores and standard I/O IP.
- Collaborate with physical design, software, and silicon bring-up teams.
- Prepare technical documentation and support design reviews and handoffs.
Requirements
Core technical skills and expectations.
- Experience with ASIC design flow: RTL coding, debugging/verification, synthesis, and timing closure.
- Working knowledge of ARM cores and common I/O interfaces.
- Practical SoC architecture and micro-architectural development experience.
- Familiarity with emulation, debug, and silicon bring-up processes.
- Strong communication, documentation, organizational, and time-management skills.
Nice-to-have: hands-on experience with Ethernet, DDR, DMA, PCIe, SATA and prior technical leadership.
Education Requirements
Not specified.
About the Company
Company: TekWissen
Headquarters: Ann Arbor, MI, USA
TekWissen is a global workforce management and staffing solutions provider headquartered in Ann Arbor, Michigan. The company offers strategic talent acquisition, workforce management, and consulting services to clients worldwide.
