ASIC/RTL Design Engineer II
Infobahn SoftworldJob Title
ASIC/RTL Design Engineer II
Role Summary
Onsite engineering role contributing to RTL and SoC design in advanced digital CMOS processes. The engineer will work across chip definition, micro-architecture, RTL implementation, verification, synthesis, and timing closure.
This is a 12-month engagement supporting collaboration with physical design, software, and silicon bring-up teams.
Experience Level
Mid-level (Engineer II). Years of experience not specified.
Responsibilities
Core responsibilities include:
- Lead and participate in SoC RTL design and implementation.
- Define chip features; develop and model architecture and micro-architectural specifications.
- Convert micro-architectural specifications into RTL/logic; support synthesis and timing closure.
- Plan and execute verification, emulation, and debug activities.
- Interface with physical execution, software, and silicon bring-up teams.
- Work with IP including ARM cores, Ethernet, DDR, DMA, PCIe, SATA, and customer internal IPs.
Requirements
Must-have skills and experience:
- Hands-on experience with industry ASIC design flow: RTL coding, debugging/verification, synthesis support, and timing closure.
- Working knowledge of ARM cores and common I/O interfaces.
- Strong communication and documentation skills.
- Good organization, time management, and multitasking abilities.
- Self-driven with initiative and demonstrated technical leadership.
Contract duration: 12 months. Work type: onsite in San Jose, CA.
Education Requirements
Not specified.
About the Company
Company: Infobahn Softworld
IT services and staffing firm specializing in software development and engineering recruitment, including embedded systems and ASIC/RTL design contract placements.
