ASIC RTL Design Engineer

Job Title

ASIC RTL Design Engineer

Role Summary

Design and implement RTL for system-on-chip (SoC) projects, working across architecture, micro‑architecture, RTL coding, verification, synthesis support, timing closure, and silicon bring-up. The role involves collaborating with physical design, software, and validation teams and working with common IP blocks.

Experience Level

Mid-level. The posting does not specify a years-of-experience requirement.

Responsibilities

Primary responsibilities include translating architecture into RTL, verifying and closing timing on designs, and coordinating with cross-functional teams. Typical duties:

• Develop RTL from micro-architectural specifications and implement logic for SoC subsystems.
• Perform RTL verification, debugging, emulation, and support for silicon bring-up.
• Collaborate on chip definition, architecture modeling, and interface specifications.
• Support synthesis and timing closure activities and interface with physical design teams.
• Work with standard IP and interfaces (ARM cores, Ethernet, DDR, DMA, PCIe, SATA, and internal client IPs).
• Document designs and communicate progress and issues to stakeholders.

Requirements

Must-have skills and experience, followed by desirable attributes.

• Must-have: Practical industry experience in ASIC design flow including RTL coding, RTL debugging and verification, and supporting synthesis and timing closure.
• Must-have: Knowledge of SoC architecture and hands-on experience with common IP (ARM cores and standard I/O interfaces).
• Desirable: Experience with Ethernet, DDR, DMA, PCIe, SATA, and other SoC IP blocks.
• Desirable: Technical leadership, good documentation and communication skills, strong organization and time-management, and ability to multitask.

Education Requirements

Not specified.

About the Company

Company: VIVA USA

Technology and staffing company providing engineering and IT workforce solutions, including recruiting and placing technical professionals such as ASIC/SoC design and RTL engineers.