ASIC/RTL Design Engineer

Job Title

ASIC/RTL Design Engineer

Role Summary

Engineer responsible for low-power design strategies, synthesis, static timing analysis, and power/timing closure for complex SoC and IP. Works with RTL designers, physical design, and verification teams to meet power, performance, and area (PPA) targets and sign-off requirements.

Experience Level

Mid-level. Suitable for engineers with practical ASIC RTL, synthesis, and STA experience.

Responsibilities

Core responsibilities include:

• Develop and apply power reduction strategies across SoC and IP designs.
• Perform synthesis and static timing analysis to achieve PPA targets.
• Analyze and optimize dynamic and leakage power using industry EDA tools.
• Collaborate with RTL, physical design, and verification teams to meet timing and power requirements.
• Run low-power verification checks (UPF/CPF) and validate power intent implementation.
• Support sign-off activities for lint, CDC, synthesis, timing, and power closure.
• Automate and streamline power and timing workflows and build test-plan documentation.

Requirements

Must-have technical skills and experience:

• Strong background in ASIC synthesis and static timing analysis (STA).
• Hands-on experience with EDA tools (examples: Synopsys Design Compiler, PrimeTime, PrimePower, Power Artists or equivalent).
• Experience with power analysis and optimization techniques (clock gating, multi-Vt, power gating, multi-voltage design).
• Familiarity with UPF/CPF power intent specification and verification.
• Solid understanding of digital design fundamentals and RTL coding (Verilog/SystemVerilog).
• Proficiency in scripting for flow automation (TCL, Perl, Python, or Shell).

Nice-to-have:

• Experience with advanced process nodes (7nm, 5nm, 3nm).
• Exposure to floorplanning, place-and-route, ECO flows, or graphics pipeline knowledge.
• Prior leadership, mentorship, or cross-functional collaboration experience.
• Experience with C/C++ and automating workflows in distributed compute environments.

Education Requirements

Not specified.

About the Company

Company: VIVA

Headquarters: Santa Clara, CA, USA

VIVA is a semiconductor company focused on developing low-power SoC and IP solutions, emphasizing power, performance, and area (PPA) optimization using industry-standard EDA tools and low-power design methodologies.