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ASIC Research Engineer - Front-End Digital Design

University of Southern California
October 26, 2026
Full-time
On-site
Arlington, Virginia, United States
RTL Design Jobs, Level - Mid-Career

Job Title

ASIC Research Engineer - Front-End Digital Design

Role Summary

The USC Information Sciences Institute (ISI) CS&T Division in Arlington, VA seeks an engineer to design and verify front-end digital ASIC prototypes for communications, signal processing, and security applications. The role works with research sponsors and a multidisciplinary team to move RTL designs through verification, synthesis, and prototyping.

Experience Level

Mid-level. The role typically expects 3+ years of relevant experience in digital design or a related discipline.

Responsibilities

Contribute to front-end digital ASIC projects, from RTL development to prototype verification and handoff for fabrication.

  • Design and verify RTL models for CPUs, memories, and hardware accelerators (Verilog/SystemVerilog/VHDL).
  • Integrate third-party IP cores and work with MOSIS/MPW flows for prototyping.
  • Perform logic synthesis, static timing analysis, and performance modeling for designs.
  • Develop and run verification environments and FPGA prototypes to validate functionality.
  • Use EDA tools, scripting, and revision-control systems to manage design data and automation.
  • Collaborate with researchers, sponsors, and cross-functional engineers in a fast-paced research setting.

Requirements

Must-have technical skills and eligibility related to the role. Degree requirements are summarized under Education Requirements below.

  • U.S. Citizenship or Permanent Residency required to handle Controlled Unclassified Information (CUI).
  • Proven experience implementing digital designs using Verilog, SystemVerilog, or VHDL.
  • Solid understanding of computer architecture and microarchitecture.
  • Experience with EDA tools, scripting (e.g., Python, Tcl), and revision control (e.g., Git).
  • Familiarity with logic synthesis and static timing analysis tools.
  • Experience with FPGA development and Linux-based toolchains.
  • Ability to work in agile hardware design workflows and adopt AI-assisted tools for design and verification.

Education Requirements

Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field with over 3 years of relevant experience, or a Master's degree in a related field. The posting implies equivalent practical experience may be considered when aligned with the stated experience level.


About the Company

Company: University of Southern California

Headquarters: Los Angeles, CA, USA

A private research university based in Los Angeles. USC’s Viterbi School of Engineering includes the Information Sciences Institute (ISI), which conducts sponsored research and development in computing, communications, artificial intelligence and advanced information processing, and builds prototypes and systems for government and industry partners.

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Date Posted: 2026-10-23