ASIC Physical Design Staff Engineer

Job Title

ASIC Physical Design Staff Engineer

Role Summary

Senior back-end physical design engineer responsible for end-to-end RTL-to-GDSII implementation and sign-off for memory test-chip blocks and top-level designs. Work with Front-End, CAD, DFT, STA, and Foundry teams to deliver manufacturable tape-outs and reusable automation.

Experience Level

Senior-level; requires 5+ years of hands-on ASIC physical design experience with proven silicon tape-outs.

Responsibilities

Primary responsibilities include implementation, verification, sign-off, and automation:

• Own full RTL-to-GDSII flow for memory test-chip blocks and top-level designs: synthesis, floorplanning, power planning, placement, CTS, routing, and sign-off closure.
• Develop and maintain PnR, STA, PV, IR/EM analysis, and extraction methodologies.
• Review and implement foundry sign-off requirements and tape-out checklists to ensure manufacturing compliance.
• Execute timing analysis and closure across multiple PVT corners, optimizing for power, performance, and area.
• Drive physical and electrical verification using IC Validator; resolve DRC, LVS, ERC, antenna, EM, IR-drop, and signal-integrity issues.
• Collaborate with Foundry, CAD, Front-End, DFT, and STA teams to resolve implementation challenges and meet milestones.
• Build automation frameworks and reusable scripts in Python, Tcl, and Perl to improve design productivity and flow efficiency.

Requirements

Must-have technical skills and experience:

• 5+ years of hands-on ASIC physical design experience with proven silicon tape-outs.
• Deep expertise across the full RTL-to-GDSII implementation flow: synthesis, floorplan, power planning, placement, CTS, routing, and sign-off.
• Proficiency with Synopsys tools such as Fusion Compiler / ICC2, PrimeTime, StarRC, and IC Validator.
• Strong scripting and automation skills in Tcl, Python, and Perl with a track record of building flows others can use.
• Experience setting up and maintaining back-end sign-off methodologies including PnR, STA, PV, extraction, and IR/EM analysis.
• Ability to interpret and implement foundry sign-off requirements and tape-out checklists to ensure manufacturing readiness.

Nice-to-have:

• Experience on advanced process nodes and memory design implementations.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.