ASIC Physical Design Staff Engineer
Lead the physical implementation of high-speed mixed-signal IP from RTL to GDSII within the Synopsys Mixed-Signal IP organization. Work across front-end, analog, CAD, and product teams to deliver signoff-clean physical designs that meet timing, power, and area targets.
Senior-level role. Expectation: 8+ years of hands-on physical design experience in ASIC or IP development.
Primary responsibilities include owning physical implementation and mentoring team members.
Must-have technical skills and domain experience. Education details are summarized separately below.
Bachelor's or Master's degree in Electrical Engineering. The posting specifies 8+ years of hands-on physical design experience; no alternative-equivalent-experience language was provided.
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
