ASIC Physical Design Staff Engineer

Job Title

ASIC Physical Design Staff Engineer

Role Summary

Staff-level physical design engineer responsible for end-to-end RTL-to-GDSII implementation of UCIe IP on advanced process nodes (7nm, 5nm, 3nm). The role sits on the back-end/physical design team in Da Nang and collaborates with front-end designers, verification, packaging, and foundry partners to deliver tape‑out quality designs.

This is a hands-on engineering role focused on timing closure, power delivery, signal integrity, physical verification, and automation to meet demanding latency, bandwidth, and power targets for die-to-die interfaces.

Experience Level

Senior (Staff-level). Posting specifies 3 to 10+ years of ASIC physical design experience; ideal candidates have multiple advanced-node tape-outs.

Responsibilities

The candidate will own physical implementation tasks from synthesis through sign-off and produce tape-out packages for UCIe IP blocks.

• Lead RTL-to-GDSII flow: synthesis, floorplanning, power grid architecture, placement, CTS, routing, and sign-off closure at advanced nodes.
• Close timing across multiple PVT corners and operating modes, optimizing latency, bandwidth, area, and power trade-offs.
• Perform physical and electrical verification (DRC, LVS, ERC), and mitigate electromigration, IR-drop, and signal integrity issues.
• Design and validate bump and pad-ring layouts and coordinate constraints with package teams for die-to-die interfaces.
• Develop and maintain automation scripts to streamline back-end flows and reduce manual bottlenecks.
• Prepare tape-out deliverables: GDSII databases, foundry checklists, and required documentation for sign-off.

Requirements

Key technical must-haves and preferable skills for immediate contribution.

• Must-have: 3+ years hands-on ASIC physical design experience with RTL-to-GDSII ownership and advanced-node tape-out experience (7nm/5nm/3nm preferred).
• Must-have: Deep experience with die-to-die interfaces (UCIe, HBM, high-speed DDR) including timing, power, and SI considerations.
• Must-have: Proficiency with Synopsys physical design and sign-off tools such as IC Compiler II / Fusion Compiler and PrimeTime; experience with IC Validator for physical verification.
• Must-have: Strong scripting/automation skills in Python, Tcl, Perl, or Shell to build and maintain flows.
• Nice-to-have: Demonstrated ability to set physical-design methodologies and improve tape-out cycle time across teams.
• Nice-to-have: Prior experience working across time zones with front-end, verification, and package teams on chiplet or multi-die projects.

Education Requirements

Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field (explicitly listed in the posting).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.