ASIC Physical Design Sr. Engineer
SynopsysJob Title
ASIC Physical Design Sr. Engineer
Role Summary
The role involves implementing advanced DDR IP solutions for silicon chips and ensuring timing closure at cutting-edge technology nodes. The engineer will collaborate within a team focused on physical design in a dynamic and multicultural environment.
Experience Level
Senior level with 3+ years of experience in ASIC physical design.
Responsibilities
The key responsibilities include:
- Implementing and integrating DDR IPs at advanced nodes.
- Performing timing closure for designs operating above ~4GHz.
- Collaborating with local and US teams on technical challenges.
- Integrating mixed-signal macro IPs and optimizing placement.
- Designing efficient clock trees to meet stringent requirements.
- Driving improvements in implementation methodologies.
- Participating in design reviews and providing innovative feedback.
Requirements
The following requirements are essential:
- Strong technical concepts with 3+ years in ASIC physical design.
- Experience with DDR IP implementation and timing closure at advanced nodes.
- Proficiency in EDA tools for synthesis and timing analysis.
- Expertise in clock tree synthesis and skew balancing.
- Experience with mixed-signal macro IPs integration.
- Ability to work collaboratively with diverse teams.
Education Requirements
Not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
