ASIC Physical Design Senior Staff Engineer

Job Title

ASIC Physical Design Senior Staff Engineer

Role Summary

Lead block- and chip-level physical design activities from netlist through final implementation (RTL to GDSII). Provide technical leadership, mentor junior engineers, and drive improvements in methodology, automation, and cross-functional delivery for complex SoC hardening.

The role sits on an implementation-focused engineering team working closely with RTL, DFT, packaging, MBIST and foundation IP teams to deliver manufacturable, high-quality silicon on schedule.

Experience Level

Senior-level (technical lead / senior individual contributor). Years of experience not specified.

Responsibilities

Primary responsibilities include leading physical design execution, ensuring signoff closure, and improving flows and automation.

• Lead block- and chip-level physical design from RTL to GDSII, including floorplanning and power planning.
• Perform placement, clock tree synthesis, and routing optimization for timing, power, area, congestion, and signal integrity.
• Execute signoff timing, EMIR and physical verification analysis and closure; implement ECOs as required.
• Drive floorplan and macro placement, special routing and ESD considerations to meet customer requirements.
• Collaborate with cross-functional teams (implementation, DFT, packaging, foundation IPs, MBIST) to meet hardening and tape-out goals.
• Develop and improve automation scripts and methodologies to increase efficiency and quality.
• Investigate and resolve design, tool, flow, and machine issues throughout implementation.
• Mentor junior engineers and provide technical leadership across the team.

Requirements

Must-have technical skills and expectations for successful candidates.

• Strong experience in ASIC physical design and implementation, including full physical flow, optimizations, and signoff closure.
• Experience with advanced process nodes and complex SoC IP integration challenges.
• Strong understanding of STA, EMIR, and physical verification concepts.
• Proficiency with industry-standard implementation and signoff tools such as Synopsys Fusion Compiler, PrimeTime, RedHawk, ICV, or similar.
• Scripting experience (Python, Tcl, Perl, bash) and familiarity with makefiles and version control systems.
• Excellent written and verbal communication skills in English and proven ability to work effectively in cross-functional teams.
• Demonstrated problem-solving, attention to detail, and ability to drive design closure under schedule constraints.
• Nice-to-have: experience with packaging, MBIST, DFT, and previous mentoring or technical leadership roles.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related field — or equivalent practical experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.