ASIC Physical Design Manager
SynopsysJob Title
ASIC Physical Design Manager
Role Summary
Lead a global physical-design team responsible for the complete backend flow from RTL handoff through tape-out for high-speed die-to-die interconnect chips. Own timing closure, floorplanning, power and clock-tree strategies, and collaborate with architecture, design, verification, and package teams to meet product requirements and milestones.
Drive methodology, automation, and tool flows for advanced nodes (7nm/5nm/3nm) to ensure first-pass silicon success and reliable high-frequency operation.
Experience Level
Senior — requires 10+ years of hands-on physical-design experience and demonstrated experience managing and mentoring engineering teams.
Responsibilities
Key responsibilities include technical leadership of physical implementation, delivery of tape-outs, and process improvement.
- Lead the full physical-design flow (floorplanning, power planning, CTS, P&R, physical verification) for advanced-node designs.
- Own timing closure across corners and modes; work with front-end teams to resolve critical paths and ensure SI/PI integrity.
- Build, manage, and mentor a distributed physical-design team; set technical direction and develop engineers at multiple levels.
- Collaborate with architecture, design, verification, and packaging teams to align implementation with product requirements and schedules.
- Drive automation and methodology improvements using scripting and flow development to increase productivity and quality.
- Deliver multiple successful tape-outs and ensure first-pass silicon success on high-frequency interconnect chips.
Requirements
Must-have technical skills, tools, and experience. Education requirements are summarized separately below.
- Must-have: 10+ years of hands-on physical-design experience with leadership responsibility.
- Must-have: Multiple successful tape-outs on advanced process nodes (7nm, 5nm, 3nm) and experience with high-frequency designs (2 GHz+).
- Must-have: Expert proficiency with Synopsys physical-design tools such as ICC2, Fusion Compiler, PrimeTime, StarRC, and RedHawk.
- Must-have: Strong scripting and automation skills (Tcl, Python, Perl) for flow development.
- Must-have: Deep understanding of timing closure, SI/PI issues, and how physical decisions impact yield and schedule.
- Must-have: Proven ability to manage multiple tape-outs across geographies and to mentor engineers into technical leaders.
- Nice-to-have: Experience shaping physical-design tool flows and organization-wide methodology standards.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field; PhD is a strong plus. (No explicit equivalent-experience language provided.)
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
