ASIC Physical Design Engineer

Job Title

ASIC Physical Design Engineer

Role Summary

Join Tektronix (a Ralliant company) as an ASIC Physical Design Engineer working on full-chip and subsystem physical implementation for next-generation SoC devices. The role executes RTL-to-GDSII physical design flows, collaborates with RTL, verification, DFT, analog, packaging, and product teams, and delivers manufacturable, tapeout-ready designs.

Experience Level

Mid-level. Minimum 5+ years of hands-on ASIC physical design experience; 10+ years expected for principal-level responsibilities.

Responsibilities

Key responsibilities include:

• Execute digital physical implementation from RTL or gate-level netlist through GDSII: floorplanning, placement, clock tree synthesis, routing, and design closure.
• Run place-and-route flows and optimize for timing, power, area, signal integrity, and routability using industry EDA tools.
• Perform static timing analysis and multi-mode multi-corner timing verification; resolve setup, hold, clocking, and constraint issues.
• Support physical signoff activities: DRC, LVS, extraction, IR drop, electromigration, and signal integrity checks.
• Collaborate with cross-functional teams to resolve implementation issues and improve design hand-off quality.
• Develop and maintain scripts, automated flows, documentation, and review materials to improve methodology and predictability.

Requirements

Must-have technical skills and experience:

• 5+ years hands-on ASIC/SoC physical design experience executing RTL-to-GDSII flows.
• Practical experience with floorplanning, power planning, place-and-route, clock tree synthesis, routing, and ECOs.
• Proven ability with static timing analysis, timing constraints, and timing closure at block or SoC level.
• Familiarity with physical signoff debug activities (DRC, LVS, extraction, IR drop, electromigration, crosstalk).
• Proficiency with industry-standard physical design and timing tools (Cadence, Synopsys, Siemens EDA, or equivalent).
• Strong scripting and automation skills (Tcl, Python, Perl, or shell) to support flows and reporting.
• Basic knowledge of ECO practices and the ability to provide feedback to RTL and packaging teams to improve hand-offs.
• Ability to work on-site in the listed locations and comply with U.S. export control requirements (candidates must be U.S. Persons or able to obtain required authorizations).

Nice-to-have:

• Principal-level experience leading physical design for complex SoC programs and managing external design service providers.
• 10+ years hands-on physical design experience and advanced expertise in clocking methodology, ECO implementation, and tapeout-quality delivery.

Education Requirements

Required: BS in Electrical Engineering or equivalent practical experience. Preferred: MS or PhD in Electrical Engineering (or equivalent experience). The posting allows equivalent practical experience in lieu of a degree.

About the Company

Company: Ralliant

Headquarters: Beaverton, OR, United States

Ralliant is a public precision-technology company that designs and manufactures high-performance instruments, sensors, and subsystems for engineering and industrial applications. It is the parent company of Tektronix and focuses on enabling measurement and test solutions across industries.