ASIC Physical Design Engineer
NVIDIAJob Title
ASIC Physical Design Engineer
Role Summary
The ASIC-PD team is hiring junior engineers to work on physical design from RTL to GSDII. You will perform design quality checks and collaborate with teams on physical applications. The role includes various tasks within the advanced process and technology domains.
Experience Level
Entry-level, 1+ year experience preferred.
Responsibilities
Your responsibilities will include:
- STA for hierarchical design.
- Creation and validation of constraints, timing budget.
- Timing closure for partition and full chip levels.
- Special timing closure for IO, test, clock, etc.
- Synthesis, netlist quality check, formal verification.
- Chip partition implementation and floorplan design.
- Function ECO creation.
- Develop timing closure flow from frontend to backend.
- Flow automation development and methodology enhancement.
Requirements
We require the following qualifications:
- MS in EE, CS, or Microelectronics with 1+ year experience preferred.
- Project experience in IC design implementation.
- Courses in circuit and digital design.
- Hands-on experience with EDA software from Synopsys and Cadence.
- Proficient in Python, Perl, or TCL.
- Proficient in English reading and writing.
Education Requirements
MS in Electrical Engineering, Computer Science or Microelectronics.
About the Company
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
