ASIC Packaging Signal & Power Integrity Technical Lead

Job Title

ASIC Packaging Signal & Power Integrity Technical Lead — Hardware Engineering

Role Summary

Lead signal and power integrity engineering for ASIC packaging within Cisco's Common Hardware Group, focused on high-performance switching, routing, and wireless platforms. Drive SI/PI architectures, package design rules, and cross-team technical decisions from concept through high-volume release.

Work with layout, system, and vendor partners to optimize interposer, substrate, and PCB solutions. Remote options are available for U.S. residents; the role is aligned with the San Jose hardware engineering organization.

Experience Level

Senior technical lead. Typical experience: 8+ years in SI/PI or related hardware engineering (senior-level responsibility for architecture and mentoring).

Responsibilities

Primary responsibilities include technical leadership, design validation, and cross-team coordination for ASIC packaging SI/PI.

• Define and implement ultra-high-speed signaling and power design rules to meet power, performance, and area targets.
• Perform substrate SI/PI analysis and collaborate with layout teams to optimize interposer, substrate, and PCB designs.
• Lead package design and release activities, including post-layout extraction, reporting, and physical validation.
• Drive cross-functional technical problem solving with system partners, vendors, and IC design teams.
• Define processes, methods, and tool flows for complex ASIC and package developments.
• Review chip architecture and complex IC/analog-mixed-signal designs for SI/PI implications.
• Mentor junior engineers and promote design reviews, postmortems, and continuous improvement.

Requirements

Key technical skills and experience required or strongly preferred.

• Must-have: Expertise in high-speed signaling principles (transmission line theory, impedance networks) and practical experience with 56G PAM4 SerDes architectures.
• Must-have: Hands-on pre- and post-layout SI/PI simulation experience using EDA tools such as Cadence Sigrity and Ansys HFSS.
• Must-have: Experience with layout reviews and physical design validation using Cadence APD and Ansys EM flows.
• Must-have: Circuit-level analysis and signal modeling experience (SPICE or equivalent).
• Must-have: Proven ability to lead technical discussions and resolve complex cross-domain SI/PI issues.
• Nice-to-have: Experience with high-speed memory interface SI and die-to-die interfaces (UCIe or proprietary).
• Nice-to-have: Familiarity with advanced packaging techniques such as CoWoS and EMIB and high-volume package release processes.

Education Requirements

Bachelor's degree in Electrical Engineering with ~8+ years relevant experience; Master's degree with ~6+ years; or PhD with ~3+ years in signal and power integrity or closely related fields (electrical engineering, computer engineering, physics). No specific certifications were listed.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).