ASIC Implementation Project Engineering Management, Senior Staff

Job Title

ASIC Implementation Project Engineering Management, Senior Staff

Role Summary

Lead and deliver physical-design implementation of DDR, HBM, and UCIe PHY hardening projects from floorplan through tapeout for advanced FinFET process nodes. Act as the primary technical interface to customers and internal R&D, translate constraints into executable implementation plans, and ensure project quality and timely delivery.

Experience Level

Senior — requires extensive experience (12+ years) in ASIC/SoC physical design and project leadership.

Responsibilities

The role combines hands-on implementation, customer-facing technical leadership, and program-quality governance.

• Oversee physical design implementation of DDR, HBM, and UCIe PHYs from floorplan through tapeout in FinFET nodes (7nm and below).
• Analyze customer requirements and produce technical solutions addressing floorplan, bump mapping, DFT strategy, packaging, and process constraints.
• Serve as the primary technical interface with customers and internal R&D; translate constraints into executable design plans and run technical reviews.
• Enforce quality management practices: author project documentation, run design reviews, and certify delivery checklists.
• Work hands-on with physical implementation and signoff tools (IC Compiler II/Fusion Compiler, PrimeTime, StarRC) to diagnose and resolve critical issues.
• Feed field implementation learnings back into IP R&D to improve product roadmaps and methodologies.
• Prepare technical presentations and deliverables for customers, sales, and internal stakeholders.

Requirements

Must-have technical skills and experience to perform the role; listed concisely.

• 12+ years of hands-on ASIC or SoC physical design experience, including work on critical IP blocks.
• Expert-level proficiency with Synopsys physical design and signoff tools: IC Compiler II, Fusion Compiler, PrimeTime, StarRC.
• Proven experience leading design teams or managing complex physical-design projects through tapeout.
• Direct implementation experience in FinFET nodes at 16nm or below (experience at 7nm, 5nm, or 3nm preferred).
• Strong working knowledge of modern DFT concepts including scan, ATPG, and MBIST.
• Familiarity with advanced packaging technologies, particularly flip-chip and multi-die integration.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field (BS or MS).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.