ASIC Implementation Engineer

Job Title

ASIC Implementation Engineer

Role Summary

Work on top-level physical design and floorplanning for ASICs in the ASIC Products Division, focusing on AI and PCIe switch products. The role covers RTL-to-silicon implementation including floorplanning, partitioning, clock delivery, and chip-level integration.

Base salary range: $143,800 - $230,000 (annual). Eligible for discretionary bonus and equity awards.

Experience Level

Senior — requires approximately 10–12+ years of experience in top-level floorplanning and physical design; specific postings list 12+ years with a Bachelor's or 10+ years with a Master's.

Responsibilities

Primary responsibilities include top-level floorplanning, integration, and cross-functional coordination to prepare designs for tape-out.

• Own chip floorplanning, partition creation, and top-level clock delivery.
• Estimate die size, define partitions, and plan pin/bump placement.
• Resolve physical design issues related to chip integration and assembly, including DRC/LVS/EMIR problems for advanced nodes.
• Coordinate with package and methodology teams on I/O, bump planning, and RDL implementation.
• Develop and improve floorplan implementation methodologies using industry and internal tools.
• Perform technical evaluations of vendors and IP and provide assessments to meet design specifications.

Requirements

Must-have technical skills and work conditions; followed by relevant nice-to-have experience.

Must-have

• Extensive top-level floorplanning experience: die size estimation, partitioning, clocking, and pin planning.
• Experience resolving chip-level DRC/LVS/EMIR issues for advanced process nodes.
• Proven experience with bump planning, RDL implementation, and multi-voltage domain designs.
• Experience with hierarchical floorplanning, power grid design, structured clocks, and custom routes.
• Hands-on use of EDA tools for physical implementation and scripting in Python, Tcl, or Perl.
• Demonstrated cross-functional collaboration with design, package, and methodology teams during development and integration phases.
• Must work on-site at the San Jose facility (no remote option).

Nice-to-have

• Experience with high-speed SERDES, HBM, D2D I/O, chiplets, switch fabric, arbiters, and high-speed DDR interfaces.
• Experience evaluating third-party IP and vendor flows for large ASICs.

Education Requirements

Preferred: Bachelor's degree in Electrical Engineering with 12+ years of relevant top-level floorplanning/physical design experience, or Master's degree in Electrical Engineering with 10+ years of such experience, as stated in the posting.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.