ASIC/FPGA Verification Engineer (UVM / SystemVerilog)

Job Title

ASIC/FPGA Verification Engineer (UVM / SystemVerilog)

Role Summary

Onsite verification engineer responsible for developing SystemVerilog/UVM testbenches to verify ASICs and FPGAs. The role works with hardware, system, and firmware teams to capture requirements, run simulations and hardware bring-up, and close functional and code-coverage gaps.

Location: Mountain View, CA (role may also be based in El Segundo, CA or Mesa, AZ). Shift: First (8:00 AM–5:00 PM).

Experience Level

Mid-level. Posting cites 2+ years for associate-level or 5+ years for experienced verification engineers.

Responsibilities

Core responsibilities include verification, automation, and hardware support.

• Write SystemVerilog/UVM testbenches and self-checking UVM components (drivers, monitors, scoreboards, sequencers).
• Develop functional coverage models and drive code-coverage closure.
• Create tests validating DSP and third-party IP integration.
• Run simulations, linting, clock-domain-crossing (CDC) checks, static timing checks, and gate-level regressions.
• Automate flows using scripting (Python/Perl/Make) and revision control (git/svn).
• Support FPGA bring-up, hardware emulation/prototyping, and hardware integration testing.
• Collaborate with system and hardware teams to capture requirements and debug issues.

Requirements

Must-have technical skills and experience.

• Experience with ASIC/FPGA verification using SystemVerilog and UVM.
• Ability to build self-checking testbenches and use object-oriented SystemVerilog features.
• Familiarity with functional coverage and code-coverage closure processes.
• Comfortable working in Linux and using scripting tools for automation.
• Experience running simulation flows, linting, CDC checks, static timing, and gate-level regressions.
• Experience with revision control systems (git or svn).

Preferred:

• 2+ years (associate) or 5+ years (experienced) verification experience.
• Experience with hardware emulators (e.g., Palladium) and FPGA prototyping.
• Knowledge of high-speed SerDes (PCIe, Ethernet, JESD204C).
• Experience with SystemVerilog Assertions (SVA) and RTL-to-GDS flows.
• Familiarity with space/radiation mitigation techniques is a plus.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.

About the Company

Company: Indotronix Avani Group

Engineering services firm providing FPGA/ASIC design and verification support for high‑reliability and military systems (e.g., GPS). Offers contract engineering across requirements capture, digital architecture, RTL design (VHDL/Verilog), verification (SystemVerilog/UVM), timing closure, and lab integration in secure environments.