ASIC/FPGA Logic Team Lead

Job Title

ASIC/FPGA Logic Team Lead

Role Summary

Lead a small RTL design team responsible for ASIC and FPGA modules that contribute to rack-level architectures for datacenter acceleration. The role combines people management, project planning, and hands-on RTL development.

Experience Level

Senior-level. Posting requests 10+ years of hands-on ASIC or FPGA development experience.

Responsibilities

Manage and deliver RTL/IP projects while contributing technically as a designer.

• Lead and mentor a team of ~3 RTL engineers.
• Set priorities, development flow, and schedules for the team.
• Design and implement RTL (Verilog) features and modules; perform code review.
• Drive new IP/module development from specification through delivery.
• Coordinate with system architects and cross-functional teams to align module interfaces and integration.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

• 10+ years hands-on experience in ASIC or FPGA development (RTL-focused).
• Proven expertise in RTL coding using Verilog.
• Experience leading or mentoring engineers and managing delivery schedules.
• Strong problem-solving and ability to learn new technical areas rapidly.
• Collaborative team player with good communication skills.
• Nice-to-have: experience with scripting/programming in Python.

Education Requirements

Bachelor's degree in Electrical Engineering, Software Engineering, or Computer Science.

About the Company

Company: UnifabriX

Headquarters: Haifa, Israel

Stealth-mode startup developing scalable hardware and software technologies to accelerate, virtualize and transform datacenters into secure workload-centric infrastructures. Focus areas include VLSI and rack-level architectures; backed by venture capital and industry leaders.