ASIC Engineering Intern, Formal Verification

Job Title

ASIC Engineering Intern, Formal Verification

Role Summary

Join the Infrastructure Silicon team working on ASIC accelerators for data center workloads. You will apply formal verification methods and tools to IP and sub-systems, develop assertions and formal testbenches, analyze proofs and counterexamples, and work with experienced ASIC engineers on a scoped internship project.

This is a 12–16 week paid internship focused on practical formal verification of hardware designs.

Experience Level

Internship / Entry-level - intended for current students or recent students; practical internship experience expected, not a senior engineering role.

Responsibilities

Typical responsibilities during the internship include:

• Understand architecture, microarchitecture and intended behavior of designs under verification.
• Contribute to formal verification plans: identify requirements, properties to prove and scenarios to cover.
• Write SystemVerilog Assertions (SVA), assumptions and cover properties to verify functionality, protocols and corner cases.
• Develop formal testbenches and harnesses (clock, reset and environment models) with guidance.
• Run formal verification tools, analyze proof results and debug counterexamples to separate design bugs from property or environment issues.
• Improve proof convergence and assess formal coverage; check for vacuous assertions, unreachable scenarios and restrictive assumptions.
• Develop scripts to automate formal runs, regressions and results analysis; collaborate with design and verification engineers to resolve issues.

Requirements

Must-have skills and conditions; preferred items listed separately.

• Knowledge of computer architecture and digital logic fundamentals, including sequential logic and finite-state machines.
• Knowledge of a hardware description language such as Verilog, SystemVerilog or VHDL.
• Familiarity with assertion-based or formal verification concepts (properties, assumptions, counterexamples).
• Ability to think critically and creatively about verification strategies and problem solving.
• Must obtain and maintain work authorization in the country of employment at time of hire.
• Nice-to-have: experience writing SVA and using formal property-checking tools (e.g. Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal).
• Nice-to-have: familiarity with open-source formal tools (SymbiYosys, ABC, Boolector) and techniques such as bounded model checking, induction, abstraction and assume-guarantee reasoning.
• Nice-to-have: scripting for automation (Python, Tcl, Perl, Shell) and familiarity with revision control systems (Mercurial, Git, SVN).
• Nice-to-have: exposure to data-center application designs (AI/ML accelerators, networking, video processing ASICs) and experience using AI coding agents to assist development or automation workflows.

Education Requirements

Currently enrolled in or in the process of obtaining a Bachelor’s degree in Electrical Engineering, Computer Engineering or a related engineering field; intent to return to a degree program after the internship is required. A Master’s or PhD in EE/CE or related fields is preferred. (No equivalent-experience alternative was specified.)

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.