ASIC Engineer, Power

Job Title

ASIC Engineer, Power

Role Summary

Work on the EDA Infrastructure team to develop and maintain power analysis and optimization flows that enable silicon engineers to model, estimate, and reduce power in custom ASIC designs. The role spans EDA tooling, physical design, RTL, and verification to improve power signoff accuracy and turnaround.

Experience Level

Mid-level - typically requires 6+ years of relevant ASIC or physical design experience focused on power analysis and optimization.

Responsibilities

Key responsibilities include:

• Develop and maintain power analysis flows: dynamic and static power estimation, vectorless analysis, and power intent verification using industry-standard EDA tools.
• Define and implement power methodology for RTL, synthesis, and physical design stages.
• Collaborate with RTL, physical design, and verification teams to identify and resolve power hotspots and inefficiencies.
• Build and optimize automation and EDA infrastructure scripts and frameworks to improve signoff accuracy and turnaround time.
• Evaluate and integrate commercial and internal EDA tools; provide technical assessments and recommendations.
• Develop and validate power intent specifications (UPF/CPF) and ensure consistent application across flows.
• Establish power budgets, track power metrics across milestones, and communicate results and risks to stakeholders.
• Analyze results across tape-outs to drive continuous improvement of power closure methodologies.
• Provide technical guidance on power analysis best practices and partner with EDA vendors.

Requirements

Required skills and experience (degree information is under Education Requirements).

Must-have:

• 6+ years of ASIC or physical design experience focused on power analysis, power optimization, or power signoff.
• Experience developing or maintaining power analysis EDA flows (e.g., Synopsys PrimePower, Cadence Voltus, or equivalent).
• Practical experience applying power intent languages (UPF or CPF) across RTL-to-GDSII flows.
• Scripting experience in Python, Tcl, or shell for building and automating EDA workflows.
• Experience collaborating across RTL, physical design, and verification to drive power closure on complex ASIC designs.
• Ability to debug power issues and drive methodology improvements across multiple projects.

Nice-to-have:

• Experience evaluating and qualifying new EDA tools or methodologies in production silicon environments.
• Familiarity with custom or semi-custom flows for high-performance computing or data-center silicon.
• Experience with low-power techniques: clock gating, power gating, multi-voltage domain design, and DVFS.
• Background developing internal EDA infrastructure or flow automation at scale.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience. Candidates in the process of obtaining a Bachelor's are acceptable but the degree must be completed prior to joining Meta.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.