ASIC Engineer, Physical Design
Meta PlatformsJob Title
ASIC Engineer, Physical Design
Role Summary
The ASIC Engineer, Physical Design will execute full-custom physical implementation of large ASICs from floorplanning through tapeout. You will collaborate with RTL, verification, package, and board teams to deliver high-performance, power-efficient silicon for data center and infrastructure platforms.
Experience Level
Entry / Early-career - requires at least 2 years of hands-on ASIC physical design experience.
Responsibilities
Contribute to physical implementation and signoff of custom ASIC blocks and full-chip designs.
- Perform floorplanning, placement, clock tree synthesis, routing, and timing closure.
- Run static timing analysis and resolve setup/hold violations across corners and modes.
- Develop and refine physical design scripts and automated flows (Tcl/Python/shell).
- Conduct power analysis and implement power-optimization techniques (clock gating, multi-voltage domains, IR mitigation).
- Execute physical verification signoff checks (DRC, LVS, ERC) and address foundry rule issues.
- Work with package and board engineers on bump maps, PDN, and IO constraints.
- Analyze and mitigate congestion, signal integrity, and electromigration problems.
- Document physical design flows, best practices, and reusable block-level methodologies.
Requirements
Must-have technical skills and tools experience; preferred items listed separately.
- 2+ years of hands-on ASIC physical design experience, including placement, CTS, routing, and timing closure.
- Experience with industry-standard physical design tools such as Synopsys IC Compiler or Cadence Innovus (or equivalent).
- Experience performing static timing analysis using Synopsys PrimeTime or equivalent tools.
- Experience with physical verification flows and signoff (DRC, LVS) using Calibre or equivalent tools.
- Scripting experience to automate flows using Tcl, Python, or shell.
- Nice-to-have: experience with data-center/infrastructure silicon, low-power design techniques, advanced process nodes (7nm or below), and hierarchical physical design for large multi-million gate chips.
Education Requirements
Bachelor's degree (or in progress) in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience.
About the Company
Company: Meta Platforms
Headquarters: Menlo Park, California, United States
American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.
