ASIC Engineer, Physical Design

Job Title

ASIC Engineer, Physical Design

Role Summary

Join Meta's silicon engineering team to drive physical implementation of custom ASICs from floorplanning through tapeout. You will work across a full-custom silicon design flow and collaborate with RTL, verification, package, and board teams to deliver high-performance, power- and area-efficient infrastructure silicon.

Experience Level

Entry-level / Early-career (2+ years of ASIC physical design experience is required).

Responsibilities

Implement and sign off physical design tasks across the backend flow and improve physical design methodologies.

• Perform floorplanning, placement, clock tree synthesis, routing, and timing closure.
• Execute static timing analysis and resolve setup/hold violations across corners and operating conditions.
• Collaborate with RTL and logic teams to enforce design-for-physical-implementation guidelines early in the cycle.
• Develop and refine scripts and flows to automate physical design tasks and improve QoR and turnaround time.
• Conduct power analysis and implement power-optimization strategies (clock gating, multi-voltage domains, IR-drop mitigation).
• Run and interpret physical verification signoff checks (DRC, LVS, ERC) to ensure foundry compliance.
• Coordinate with package and board engineers on bump maps, power delivery networks, and IO constraints.
• Analyze and mitigate congestion, signal integrity, and electromigration issues across hierarchical blocks.
• Document physical design flows, best practices, and reusable block-level methodologies.

Requirements

Must-have hands-on skills and tools experience required for day-to-day physical design work; preferred items listed separately.

Must-have:

• 2+ years of ASIC physical design experience, including placement, CTS, routing, and timing closure.
• Experience with industry physical design EDA tools (e.g., Synopsys IC Compiler, Cadence Innovus, or equivalent).
• Static timing analysis experience using tools such as Synopsys PrimeTime or equivalent.
• Experience with physical verification flows and signoff tools (e.g., Calibre or equivalent for DRC/LVS).
• Scripting skills to automate flows (Tcl, Python, or shell).

Nice-to-have / Preferred:

• Experience with advanced process nodes (7nm or below) and complex DRC constraints.
• Familiarity with low-power techniques (multi-voltage domains, power gating, DVFS).
• Experience with hierarchical physical design for very large, multi-million gate ASICs.
• Exposure to custom data-center or infrastructure silicon from block-level to tapeout.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, or a related technical field is expected, or equivalent practical experience. If pursuing a degree, it must be completed prior to joining Meta.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.