ASIC Engineer, Implementation - Timing

Job Title

ASIC Engineer, Implementation - Timing

Role Summary

Work on Meta's Infrastructure Silicon team to design and deliver custom SoC for data center applications. The role focuses on static timing analysis and driving timing closure to meet performance, power, and area targets at advanced process nodes.

Role is based in Austin, TX and interfaces with front-end, physical design, verification, foundry, and library teams.

Experience Level

Entry-level / Early career - approximately 2 years of ASIC implementation experience in static timing analysis and timing closure.

Responsibilities

Primary responsibilities include analyzing, constraining, automating, and closing timing for complex SoC designs.

• Develop and maintain timing constraints (SDC), including clock definitions and I/O delays.
• Perform static timing analysis to identify and resolve timing violations across corners.
• Collaborate with physical design engineers to drive timing closure and advise on placement and routing.
• Analyze and debug timing paths across multiple clock domains and identify critical paths.
• Generate and validate timing reports for sign-off across process, voltage, and temperature corners.
• Develop and maintain timing exception methodologies in coordination with design and verification teams.
• Contribute to timing-closure scripts and automation flows to improve efficiency.
• Integrate timing libraries with foundry and library teams, including standard cells and hard IP.
• Support design handoff by providing timing-aware synthesis netlists.

Requirements

Key must-have skills and relevant experience; a short list of desirable skills follows.

• Must-have: ~2 years of ASIC implementation experience focused on static timing analysis and timing closure.
• Hands-on experience with static timing analysis tools such as PrimeTime or equivalent.
• Proven experience developing and validating SDC timing constraints for complex SoC or IP designs.
• Experience with logic synthesis tools and timing-driven optimization techniques.
• Proficiency in scripting for automation (Python, Tcl, Perl).
• Ability to work with cross-functional teams including physical design, verification, and library/foundry engineers.
• Nice-to-have: RTL/design experience (SystemVerilog) and familiarity with clock-tree synthesis and other physical-design timing concepts.

Education Requirements

Currently pursuing or holding a Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field; equivalent practical experience is acceptable.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.