ASIC Engineer, Implementation

Job Title

ASIC Engineer, Implementation

Role Summary

Drive physical implementation and synthesis of complex custom ASICs from RTL to tape-out. Own end-to-end implementation flows, establish reusable methodology, and collaborate with architecture, RTL, verification, and physical design teams to deliver high-performance, power- and area-efficient silicon.

Experience Level

Senior - 8+ years of ASIC implementation experience (logic synthesis, static timing analysis, timing closure) is required.

Responsibilities

Primary implementation and methodology responsibilities for complex SoC or custom ASIC projects.

• Lead logic synthesis, static timing analysis, and design-for-test integration from RTL to tape-out.
• Define and own synthesis and implementation methodology, including reusable flows and constraints.
• Drive timing closure across hierarchical partitions and multi-clock-domain designs.
• Develop and maintain synthesis scripts, constraint files, and automation to reduce iteration cycles.
• Generate SOC and block-level floorplans and coordinate floorplan-driven implementation.
• Perform top-level connectivity and beachfront analysis; insert pipe/shim/feedthrough blocks for timing/area optimization.
• Provide early feedback to architecture and RTL teams on decisions that affect area, power, and timing.
• Define design-rule and sign-off criteria and ensure readiness for tape-out.
• Identify and mitigate cross-functional implementation risks and report trade-offs to stakeholders.
• Mentor engineers on synthesis best practices, timing analysis, and implementation methodology.

Requirements

Must-have technical skills and experience.

• 8+ years of ASIC implementation experience, including timing closure for complex SoC or custom ASIC designs.
• Proven experience with industry synthesis/implementation EDA tools (examples: Synopsys Design Compiler, Synopsys Fusion Compiler, Cadence Genus).
• Practical experience defining and managing synthesis constraints and hierarchical methodologies (SDC, UPF).
• Experience resolving timing closure for multi‑million gate designs with multiple clock domains and complex timing exceptions.
• Experience developing and maintaining implementation automation using scripting languages such as Tcl or Python.

Nice-to-have:

• Experience evaluating and integrating new EDA tools or methodologies into production flows.
• Familiarity with physical-aware synthesis and early floorplan co-design to improve PPA.
• Track record leading tape-out execution and defining implementation sign-off criteria.
• Experience targeting data-center, AI accelerator, or high-performance computing ASICs.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.