ASIC Engineer, Implementation

Job Title

ASIC Engineer, Implementation

Role Summary

Implement complex custom ASICs from RTL to tape-out for infrastructure and compute applications. The role focuses on synthesis, place-and-route, timing closure, physical verification, and power optimization for advanced process nodes.

Work on the Infrastructure Silicon team and collaborate with RTL designers, architects, verification, package, and board engineering to deliver high-performance, power-efficient silicon.

Experience Level

Mid-level — typically 6+ years of professional experience in ASIC physical implementation and production tape-outs.

Responsibilities

Primary tasks and ownership areas for the role.

• Lead physical implementation flows: synthesis, floorplanning, place-and-route, clock tree synthesis, and timing closure.
• Perform static timing analysis and timing signoff across multiple process corners and operating conditions.
• Develop and maintain implementation scripts, runsets, and automation to improve quality of results and turnaround time.
• Collaborate with RTL designers and architects to resolve timing, area, and power trade-offs early in the design cycle.
• Perform power analysis and implement low-power strategies (clock gating, multi-voltage domains, dynamic power reduction).
• Execute physical verification flows including DRC, LVS, and antenna checks and coordinate foundry signoff.
• Partner with package and board engineers to define chip IO constraints, bump maps, and signal integrity requirements.
• Provide technical guidance on implementation methodology, tool usage, and design-for-manufacturability.
• Analyze and communicate implementation results, risks, and trade-offs to cross-functional stakeholders.

Requirements

Must-have and preferred qualifications for successful candidates.

• Must-have: 6+ years of ASIC physical implementation experience including synthesis, place-and-route, and timing closure on production tape-outs.
• Must-have: Experience with static timing analysis and timing signoff using tools such as Synopsys PrimeTime, Cadence Tempus, or equivalent.
• Must-have: Experience with physical verification flows (DRC, LVS, antenna correction) in advanced process nodes (7nm or below).
• Must-have: Scripting and automation experience using Tcl, Python, or equivalent.
• Must-have: Experience with power analysis and low-power implementation techniques, including multi-voltage domain design and power intent specification.
• Nice-to-have / Preferred: Knowledge of timing/physical libraries, SRAM memories, clock/reset domain crossing, and LEC.
• Nice-to-have / Preferred: Experience with Design Compiler, Spyglass, PrimeTime, Formality, or equivalent EDA tools.
• Nice-to-have / Preferred: RTL familiarity (Verilog/SystemVerilog), synthesis background, floorplanning, STA, and PPA analysis techniques.
• Nice-to-have / Preferred: Additional scripting experience (Perl, Make) and experience reducing power while meeting performance and area goals.

Education Requirements

Not specified.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.