ASIC Engineer, Implementation
Meta PlatformsJob Title
ASIC Engineer, Implementation
Role Summary
Join Meta's Infrastructure Silicon team to implement custom ASICs from RTL through tape-out. The role focuses on front-end synthesis, integration, timing closure, and working with physical design to deliver high-performance, power-efficient chips for data center and compute infrastructure.
Experience Level
Entry-level / Early Career — the role expects about 2+ years of relevant front-end ASIC synthesis and integration experience.
Responsibilities
Work across synthesis, timing, and integration to deliver optimized gate-level designs and support cross-functional handoffs.
- Run RTL and physical synthesis and produce optimized gate-level netlists for timing, area, and power.
- Debug timing, area, and congestion issues and coordinate fixes with RTL and physical designers.
- Estimate power at RTL and gate level and identify reduction opportunities.
- Run formal equivalence checks between RTL and gate-level netlists and resolve failures.
- Perform RTL lint, DFT analysis, and support waiver and coverage improvements.
- Develop timing constraints for synthesis and PrimeTime STA for blocks and top-level SoC; define inter-block timing and I/O budgets.
- Create automation scripts and methodologies for front-end EDA tools (lint, CDC, synthesis, STA, power).
- Support design, verification, and emulation teams during handoff and debug cycles.
- Provide timing and congestion feedback to physical design engineers during implementation.
Requirements
Must-have technical skills and experience plus preferred capabilities.
- Must-have: 2+ years as a front-end synthesis & integration engineer or equivalent experience.
- Experience with RTL synthesis and design optimization for power, performance, and area.
- Familiarity with front-end and back-end ASIC EDA tools and flows.
- Experience with RTL design using SystemVerilog or another HDL.
- Experience managing multiple design releases and working with cross-functional teams to debug timing, area, and power issues.
- Effective communicator across internal teams and vendors.
- Nice-to-have: knowledge of physical design flow (floorplanning, CTS, routing), STA signoff (AOCV/POCV), timing/physical libraries and SRAM, EDA tools and scripting (Python, TCL), experience with Design Compiler, Spyglass, PrimeTime, Formality, low-power techniques, and SoC integration.
Education Requirements
Not specified.
About the Company
Company: Meta Platforms
Headquarters: Menlo Park, California, United States
American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.
