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ASIC Engineer, Implementation

Meta Platforms
October 26, 2026
Full-time
On-site
Sunnyvale, California, United States
Physical Design Jobs, Level - Senior

Job Title

Staff ASIC Implementation Engineer

Role Summary

Lead physical implementation and synthesis of complex custom ASICs for Meta's AI and compute platforms. Drive end-to-end implementation flows, influence architecture and RTL decisions, and deliver high-performance, power-efficient silicon.

Experience Level

Senior - the posting specifies 8 years of ASIC implementation experience.

Responsibilities

Primary responsibilities include:

  • Lead end-to-end ASIC implementation flows: logic synthesis, static timing analysis, and DFT integration.
  • Define and maintain synthesis and implementation methodology, reusable flows, and constraint standards.
  • Drive timing-closure strategies across hierarchical partitions and multi-million gate designs.
  • Develop and maintain synthesis scripts, constraint files (SDC/UPF), and automation infrastructure.
  • Generate SoC-level and block floorplans and enable block implementation owners.
  • Perform top-level logical and physical connectivity analysis for timing and area optimization.
  • Partner with architecture and RTL teams to advise on area, power, and timing trade-offs.
  • Define design rules and sign-off criteria for tape-out readiness and resolve cross-functional risks.
  • Mentor engineers on methodology and timing-analysis techniques.
  • Evaluate and recommend new EDA tools and implementation technologies.

Requirements

Must-have:

  • 8+ years of ASIC implementation experience, including logic synthesis and timing closure for complex designs.
  • Hands-on experience with EDA tools such as Synopsys Design Compiler, Fusion Compiler, or Cadence Genus.
  • Experience authoring and managing synthesis constraints (SDC) and power intent (UPF).
  • Proven track record driving timing closure on multi-million gate designs and handling complex timing exceptions.
  • Experience developing implementation automation using Tcl or Python.
  • Strong knowledge of static timing analysis and design-for-test concepts.
  • Ability to collaborate with RTL, architecture, and physical-design teams and to mentor junior engineers.

Nice-to-have:

  • Experience evaluating new EDA flows and compiler-based physical implementation technologies.
  • Prior work on AI accelerator or large SoC designs.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field (as stated).


About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.

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Date Posted: 2026-10-24