ASIC Engineer, Architecture

Job Title

ASIC Engineer, Architecture

Role Summary

Join Meta's Silicon Engineering organization to define and drive architectural performance analysis, pre-silicon modeling, and microarchitectural exploration for custom infrastructure ASICs. The role partners with architecture, RTL, physical design, and software teams to ensure silicon meets throughput, latency, and efficiency targets for hyperscale AI and data center workloads.

Experience Level

Mid-level — the role expects seniority consistent with the listed minimums (typically 6+ years in ASIC or silicon engineering and 5+ years in performance modeling).

Responsibilities

Primary responsibilities include performance modeling, microarchitectural exploration, workload development, and cross-functional coordination to translate requirements into implementable silicon designs.

• Drive microarchitectural exploration and trade-off analysis across compute, memory subsystem, interconnect, and I/O domains.
• Define and own performance modeling strategy, including cycle-accurate and transaction-level simulation environments.
• Develop and maintain C++ models of AI chip IPs and subsystems for architecture exploration and software development.
• Develop low-level workloads and kernels for ML training and inference to evaluate silicon performance.
• Establish benchmarking frameworks, bottleneck identification techniques, and performance analysis methodologies.
• Collaborate with architecture, RTL, and physical design teams to translate performance requirements into microarchitectural specifications.
• Partner with software and systems teams to co-optimize workload scheduling, firmware, and driver behavior against silicon characteristics.
• Lead technical reviews and communicate modeling results and architectural recommendations to engineering leadership.
• Define long-term modeling infrastructure roadmaps and mentor engineers on modeling and analysis best practices.
• Identify and resolve gaps between models and measured silicon through root-cause analysis and model calibration.

Requirements

Must-have technical skills and experience required to perform the role; preferred items listed separately.

• 6+ years of experience in ASIC design, silicon engineering, or a related technical field.
• 5+ years of experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designs.
• Proficiency in C++ and Python for simulation models, automation, and performance analysis tools.
• Experience with performance analysis of data center, AI accelerator, or HPC workloads on custom silicon.
• Experience developing cycle-accurate or transaction-level performance models using C++ and SystemC for complex digital systems.
• Experience defining microarchitectural specifications and driving cross-functional alignment across architecture, RTL, and physical design teams.
• Familiarity with assembly programming languages and compiler technologies.

Nice-to-have

• Experience with AI numerics, data types, and precision/accuracy analysis.
• Experience writing and optimizing compute kernels in CUDA or equivalent frameworks.
• Experience building or scaling performance modeling infrastructure for hyperscale ASICs (network, storage, inference accelerators).
• Experience developing Python automation pipelines for simulation orchestration and regression testing.
• Familiarity with post-silicon performance validation and model-to-hardware correlation.
• Experience with hardware description languages (SystemVerilog, VHDL) and HLS, and PPA-driven optimization.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.