ASIC Engineer, Architecture

Job Title

ASIC Engineer, Architecture

Role Summary

Work within Meta's Silicon Engineering organization to define and execute architectural performance analysis, pre-silicon modeling, and microarchitectural exploration for custom infrastructure ASICs used in data centers and AI workloads.

The role partners with architecture, RTL, physical design, and software teams to ensure silicon meets throughput, latency, and efficiency targets at hyperscale.

Experience Level

Senior — requires senior-level experience: 8+ years in ASIC design or silicon engineering with 5+ years focused on ASIC performance modeling or pre-silicon simulation.

Responsibilities

Primary responsibilities include building and operating performance models, driving architecture trade-offs, and guiding cross-functional design decisions.

• Define and own performance modeling strategy, including cycle-accurate and transaction-level simulation environments.
• Drive microarchitectural exploration and trade-off analysis across compute, memory subsystem, interconnect, and I/O.
• Develop and validate pre-silicon performance models that predict post-silicon behavior for data center workloads.
• Create low-level workloads and kernels for ML training and inference to exercise models.
• Establish benchmarking frameworks, bottleneck identification, and performance analysis methodologies.
• Collaborate with architecture, RTL, and physical design teams to convert performance requirements into microarchitectural specifications.
• Partner with software and systems teams to co-optimize scheduling, firmware, and drivers against silicon characteristics.
• Lead technical reviews and communicate modeling results and architectural recommendations to engineering leadership.
• Define long-term modeling infrastructure and tooling roadmaps, including automation and simulation platform investments.
• Mentor and develop other engineers on modeling techniques and analysis best practices; perform root-cause analysis to resolve model-to-hardware gaps.

Requirements

Must-have technical skills and experience are listed first; preferred skills follow.

• Must-have: 8+ years in ASIC design, silicon engineering, or related technical field.
• Must-have: 5+ years in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon/SoC designs.
• Must-have: Proficiency in C++ and Python for simulation, automation, and analysis tools.
• Must-have: Experience developing cycle-accurate or transaction-level models using C++ and SystemC for processors, memory subsystems, or high-speed interconnects.
• Must-have: Performance analysis experience with data center, AI accelerator, or HPC workloads on custom silicon.
• Must-have: Experience defining microarchitectural specifications and driving alignment across architecture, RTL, and physical design teams.
• Must-have: Experience with assembly programming languages and compiler technologies.
• Nice-to-have: Hardware description languages (SystemVerilog, VHDL) and ASIC simulation flows.
• Nice-to-have: Experience building performance modeling infrastructure for hyperscale ASICs and post-silicon validation/model-to-hardware correlation.
• Nice-to-have: Python-based automation for simulation orchestration, GPU/ML or multithreaded programming, high-level synthesis, or PPA-driven optimization.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.