ASIC Digital Verification Sr Staff Engineer

Job Title

ASIC Digital Verification Sr Staff Engineer

Role Summary

The senior/staff verification engineer will define and execute verification strategies for embedded security IP subsystems (cryptographic cores, RNGs, interfaces, memories) as part of the Security IP group in Eindhoven. The role focuses on building UVM testbenches, assertion- and formal-based verification flows, automation, FPGA validation, and working closely with design and architecture teams to ensure correct and secure silicon.

Experience Level

Senior — 6+ years of hands-on digital verification experience (as stated in the posting).

Responsibilities

Core responsibilities include:

• Design and execute verification strategies for complex security IP subsystems.
• Develop and maintain UVM testbenches, assertion-based environments, and formal verification flows.
• Create test plans, test specifications, and coverage models mapped to product requirements.
• Automate regression environments using scripting (Python, Perl, TCL) to enable continuous verification.
• Run verification in simulator environments and on FPGA platforms; perform RTL and testbench debugging and root-cause analysis with design engineers.
• Apply formal verification techniques to prove properties and reach corner cases beyond simulation.
• Support embedded software and driver verification for hardware–software integration testing.

Requirements

Must-have technical skills and experience:

• Proven track record verifying digital hardware IP components through multiple tape-outs or product releases.
• Deep expertise in SystemVerilog, UVM, assertion-based verification, and coverage-driven methodology.
• Practical experience with formal verification techniques.
• Strong understanding of IC design flows, RTL design principles, and the handoff between verification and implementation.
• Experience automating verification flows and building regression environments (Python, Perl, TCL).
• Solid knowledge of embedded hardware and software environments and how IP integrates into SoC architectures.
• Ability to debug RTL and testbench issues and communicate findings clearly to design teams.
• Effective collaboration and communication across global teams and time zones.

Nice-to-have:

• Experience with security protocols, cryptographic algorithms, or embedded security IP.
• Experience with IP synthesis flows and verifying timing and synthesis constraints.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Science; the posting specifies 6+ years of hands-on verification experience. No alternative "equivalent experience" language or certifications were listed.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.