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ASIC Digital Verification Engineer

Renesas
April 30, 2026
Full-time
On-site
Ottawa, Ontario, Canada
$76,000 - $100,000 CAD yearly
Verification Jobs, Level - Entry or Early Career
ASIC Digital Verification Engineer - Job Description

Job Title

ASIC Digital Verification Engineer

Role Summary

Join a verification team in Ottawa focused on mixed-signal digital PLL ASICs. The role centers on developing self-checking testcases, executing verification plans, analyzing coverage results, debugging simulations, and improving the verification environment and infrastructure.

The position works closely with local and remote design and verification engineers to achieve verification closure using modern methodologies and tools.

Experience Level

Entry-level; up to 2 years of relevant experience.

Responsibilities

Key responsibilities include planning and executing verification tasks and improving verification infrastructure and processes.

  • Define and implement self-checking testcases from functional requirements.
  • Contribute to verification infrastructure and automation components.
  • Plan verification activities and execute detailed verification plans.
  • Triage regressions and debug RTL and gate-level simulations.
  • Analyze functional and code coverage and drive actions to achieve closure.
  • Collaborate with design and verification teams, both local and remote.

Requirements

Must-have technical skills and attributes; nice-to-have items noted separately.

  • Must-have: Knowledge of SystemVerilog and UVM for digital verification.
  • Experience with Synopsys and/or Cadence simulation tools.
  • Experience with SystemVerilog assertions, functional coverage, and code coverage.
  • Ability to triage regressions and debug RTL and gate-level simulations.
  • Comfortable working in a Unix/Linux environment.
  • Effective communicator and team player; fast learner able to work with minimal supervision.
  • Eligible to meet applicable U.S. and Canadian export control requirements (export-license screening may be required).
  • Nice-to-have: Exposure to mixed-signal verification or PLL ASIC designs; experience improving verification infrastructure and automation.

Education Requirements

Bachelor's degree (entry level, up to 2 years of experience) or a recent Master's degree — master’s graduates with no experience are considered. No specific field of study was listed.


About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.

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Date Posted: 2026-04-09