ASIC Digital Design Staff Engineer

Job Title

ASIC Digital Design Staff Engineer

Role Summary

Lead verification ownership for Subsystem-level IP integration and verification within Synopsys' ASIC/IP organization. Drive verification strategy, develop and maintain UVM/SystemVerilog testbenches, and coordinate across design and architecture teams to achieve signoff.

This role impacts delivery of high-performance Subsystems used in AI, automotive, cloud, and mobile SoCs.

Experience Level

Senior-level. Typically requires 8+ years of ASIC/FPGA verification experience and prior technical leadership or mentoring responsibility.

Responsibilities

Lead verification strategy, testbench development, and delivery for critical Subsystem areas.

• Own verification for Subsystem areas (e.g., DDR, HBM, PCIe, UCIe, Ethernet, UALink, UFS) and drive execution with a team of verification engineers.
• Define, implement, and track detailed verification test plans that map coverage goals to silicon risk.
• Build and maintain Subsystem-level UVM testbenches in SystemVerilog, integrating RTL and models.
• Write complex test cases, assertions, and checkers; debug simulation failures to root cause.
• Extract, analyze, and close functional and code coverage gaps prior to signoff.
• Manage regression suites and improve verification flows, methodologies, and automation.
• Collaborate with RTL designers and architects across global sites to ensure functional correctness.

Requirements

Core technical skills and experience required to perform the role.

• 8+ years of hands-on ASIC/FPGA verification experience owning verification deliverables from planning through signoff.
• Expertise in SystemVerilog and UVM-based testbench development, including assertions, checkers, and constrained-random stimulus.
• Proven ability to define verification strategies, write rigorous test plans, and drive coverage closure using functional and code coverage analysis.
• Strong debugging skills for complex simulation failures and experience managing regression suites and verification metrics.
• Experience technically leading or mentoring verification engineers and collaborating across design, architecture, and verification teams.
• Clear communicator able to translate verification status for architects, designers, and project leads across time zones.
• Nice-to-have: Hands-on experience with high-speed interface protocols (DDR, HBM, PCIe, UCIe, Ethernet, UALink, UFS) and familiarity with AI-assisted verification flows.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.