ASIC Digital Design, Staff Engineer

Job Title

ASIC Digital Design, Staff Engineer

Role Summary

Senior individual contributor responsible for digital ASIC design and architecture within an ASIC design team. The role focuses on RTL design, synthesis-ready architecture, timing closure, and cross-functional coordination to deliver production silicon.

The engineer will collaborate with verification, physical design, and system teams, lead technical design reviews, and mentor junior engineers to ensure on-time, high-quality tapeout-ready designs.

Experience Level

Senior. Specific years of experience not specified in source.

Responsibilities

Key responsibilities include hands-on design work, technical leadership, and cross-team coordination.

• Develop and deliver RTL (SystemVerilog/VHDL) for complex digital blocks and subsystem architectures.
• Drive synthesis and timing closure activities, including constraints, CDC, and STA signoff collaboration.
• Work with verification and backend teams to resolve functional and timing issues through tapeout.
• Perform ECOs, timing fixes, and guide implementation of design-for-test and design-for-manufacturability practices.
• Lead design reviews, define interfaces and specifications, and ensure design meets performance, area, and power targets.
• Mentor and provide technical guidance to junior and mid-level engineers.

Requirements

Concise list of core skills and experience expected for the role.

Must-have:

• Proven experience in digital ASIC design and RTL development (SystemVerilog/VHDL).
• Hands-on experience with synthesis flows and timing analysis (constraints, STA).
• Familiarity with ASIC design toolflows and common industry tools for synthesis, timing, and verification.
• Strong debugging skills, including root-cause analysis of functional and timing failures.
• Ability to lead technical workstreams and communicate effectively with verification, backend, and system teams.
• Scripting skills for automation and flow integration (e.g., Python, TCL).

Nice-to-have:

• Experience with low-power design techniques, multi-voltage domains, and clock-gating strategies.
• Familiarity with protocol IP (DDR, PCIe, Ethernet) and system-level integration.
• Prior tapeout experience and involvement in chip signoff activities.
• Experience with Synopsys toolchain and related EDA products.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.