ASIC Digital Design Staff Engineer
SynopsysJob Title
ASIC Digital Design Staff Engineer
Role Summary
Work in the DesignWare IP Design team at the Bangalore Design Center to architect and deliver synthesizable RTL for high-speed IP (Ethernet, DDR, PCIe, USB, etc.).
Lead RTL implementation, timing closure, CDC handling and mentor designers while collaborating with global teams and customers to produce production-quality IP.
Experience Level
Senior-level - the posting specifies a minimum of 4+ years of hands-on industry ASIC RTL design experience and includes technical leadership responsibilities.
Responsibilities
Deliver RTL, drive implementation quality, and lead technical activities across the design flow.
- Architect micro-architectures from protocol specifications and produce design documentation.
- Implement synthesizable Verilog/SystemVerilog for medium-to-high complexity features (data paths, FEC, CRC, MAC SEC, etc.).
- Lead synthesis, static timing analysis, CDC analysis, lint checks, and P&R-aware synthesis to meet area, latency, and throughput targets at 600MHz+.
- Debug complex RTL issues across simulation and synthesis; resolve timing and synthesis mismatches.
- Collaborate with global engineering teams and customers to refine specifications and resolve ambiguities.
- Lead technical reviews, define test strategies, and ensure design quality and coverage.
- Mentor and technically lead RTL designers; improve coding practices and timing-closure techniques.
- Manage version control workflows and automate flows using scripting (Perforce, Perl, Shell).
Requirements
Must-have skills and experience; education is listed separately below.
- Minimum 4+ years of hands-on ASIC RTL design experience with delivered IP cores or complex digital subsystems.
- Practical expertise in data-path and control-path design, including experience with Reed Solomon FEC, BCH, CRC architectures, or MAC SEC implementations.
- Strong proficiency in synthesizable Verilog/SystemVerilog, simulation, lint, CDC analysis, synthesis, and static timing analysis.
- Experience with high-speed designs targeting 600MHz+ and P&R-aware synthesis and timing-closure techniques.
- Familiarity reading and implementing industry protocols (Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA).
- Experience with Perforce or similar version control systems and scripting for automation (Perl, Shell).
- Prior experience mentoring or serving as a technical lead is a strong plus.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering, Electronics, VLSI, or a related technical field.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
