ASIC Digital Design Staff Engineer
SynopsysRole Summary
The ASIC Digital Design Staff Engineer at Synopsys will lead verification areas within a team, focusing on the integration of advanced UCIe/Ethernet/UALink IPs in system-on-chips (SoCs). The role emphasizes technical leadership, collaboration across global teams, and ensuring high-performance silicon design through innovative verification methodologies.
Experience Level
Senior level; requires 8+ years of experience in ASIC/FPGA Verification.
Responsibilities
The key responsibilities include:
- Leading verification efforts and ownership of critical areas.
- Defining and implementing verification test plans for comprehensive coverage.
- Building and maintaining UVM-based System Verilog testbenches.
- Coding and debugging complex test cases using System Verilog/UVM.
- Managing regressions and improving verification strategies.
- Collaborating with RTL designers to ensure functional correctness.
Requirements
The ideal candidate will possess:
- Bachelor's or Master's degree in electronics or electrical engineering.
- 8+ years of experience in ASIC/FPGA Verification.
- Proven expertise with System Verilog/UVM test environments.
- Ability to extract and analyze verification metrics.
- Keen knowledge of interface protocols, especially UCIe/Ethernet/UALink.
- Experience in leading a team and mentoring peers.
Education Requirements
Bachelor's or Master's degree in electronics/electrical engineering or a related field.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
