ASIC Digital Design Sr Staff Engineer
SynopsysJob Title
ASIC Digital Design Sr Staff Engineer
Role Summary
Senior individual contributor on the DesignWare IP team in the Bangalore Design Center. You will design RTL for high-speed protocol IP (Ethernet, AMBA, PCIe, USB, MIPI, memory controllers) and drive micro-architecture, timing closure, and delivery of production-quality IP.
Work is onsite in Bengaluru and involves multi-site collaboration with verification, integration, and product teams across global locations.
Experience Level
Senior-level. The role expects substantial hands-on ASIC/IP design experience (typical hires have 8+ years of relevant experience).
Responsibilities
Primary responsibilities include designing RTL, driving timing closure, and collaborating across teams to deliver IP.
- Design and code RTL for high-speed Ethernet and other protocol IP (100G–1.6T), focusing on low latency and timing closure.
- Translate protocol specs into micro-architecture and detailed design documents for medium-complexity blocks.
- Develop and refine directed Verilog/SystemVerilog testbenches; analyze coverage and define targeted tests.
- Perform technical reviews of specs, micro-architecture, and RTL across global teams.
- Drive timing analysis and closure using synthesis, STA, lint, CDC, and formal verification flows.
- Apply low-power design techniques and automotive safety considerations where required.
- Collaborate with verification, integration, and product teams across timezones to meet delivery milestones.
Requirements
Must-have technical skills and experience.
- Deep RTL design experience on IP cores or SoC subsystems that have taped out or shipped to customers.
- Strong working knowledge of at least one protocol: AMBA (AHB, AXI, CHI), SD/eMMC, DDR, PCIe, USB, MIPI; experience with high-speed Ethernet is a strong plus.
- Proven ability to produce micro-architecture and detailed design docs for control-path and datapath blocks (async FIFOs, DMA engines, SRAM/DPRAM interfaces).
- Hands-on with Verilog or SystemVerilog, simulation tools, synthesis flows, static timing analysis, lint, CDC, and formal verification tools.
- Solid understanding of high-speed, low-latency design techniques and timing-closure challenges; datapath/arithmetic algorithm experience is beneficial.
- Familiarity with Perforce or similar version control and scripting (Perl, shell) for automation.
Nice-to-have:
- Experience with 100G+ Ethernet designs and protocols.
- Experience with FEC or other complex datapath algorithms.
- Automotive safety experience (ISO 26262) or similar safety-aware IP development experience.
Education Requirements
Bachelor's degree in Electrical Engineering (typical hire with 8+ years of ASIC/IP design experience) or Master's degree (typical hire with 6+ years of ASIC/IP design experience). No certifications specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
