ASIC Digital Design Sr Staff Engineer
SynopsysJob Title
ASIC Digital Design Sr Staff Engineer
Role Summary
The role focuses on leading verification efforts for advanced interface IPs within the Synopsys Subsystem team. The team's mission is to ensure high-quality verification and deployment of robust Subsystems that drive next-generation SoCs.
Experience Level
Senior; requires 8+ years of experience in ASIC/FPGA Verification.
Responsibilities
Key responsibilities include:
- Leading and owning critical areas of verification with a team of engineers.
- Defining and implementing comprehensive verification test plans.
- Building, enhancing, and maintaining UVM-based testbenches.
- Coding and debugging test cases using System Verilog/UVM.
- Managing regressions and improving verification strategies.
- Collaborating with RTL designers to ensure functional correctness.
Requirements
Must-have skills and qualifications:
- Bachelor's or Master's degree in electronics/electrical engineering or related field.
- 8+ years of experience in ASIC/FPGA Verification.
- Proficiency in System Verilog/UVM test environments.
- Strong debugging and verification strategy skills.
- Experience with interface protocols like UCIe/Ethernet/UALink is desirable.
- Demonstrated leadership and mentoring capabilities.
Education Requirements
Bachelor's or Master's degree in electronics/electrical engineering or related field.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
