ASIC Digital Design Senior Staff Engineer

Job Title

ASIC Digital Design Senior Staff Engineer

Role Summary

Owner-level RTL engineer responsible for architecting and delivering complex IP/subsystems from requirements through tape-out. Work closely with verification, synthesis, STA, DFT, and physical design teams to ensure first-time-right RTL for production silicon.

Experience Level

Senior — typically requires 8+ years of hands-on RTL design experience and multiple tape-outs.

Responsibilities

Design, verify, and deliver production-quality RTL for complex subsystems and IP blocks.

• Own full lifecycle: requirements, architecture, RTL development, verification collaboration, implementation handoff, and release.
• Define micro-architecture and write synthesizable, timing-clean, production RTL using industry best practices.
• Drive RTL quality checks including lint, CDC, RDC and work with verification to achieve functional correctness and coverage closure.
• Integrate and design around standard protocols (PCIe, DDR, UFS, USB, AMBA).
• Implement low-power techniques: clock gating, power gating, retention, multi-voltage domains and ensure power intent is captured and verified.
• Collaborate with logic synthesis, STA, and physical design to ensure timing closure and resolve equivalence issues.
• Architect testability features (scan, MBIST) and coordinate with DFT teams.
• Drive cross-functional planning and resolve trade-offs to meet release milestones.

Requirements

Key technical skills and practical experience required to perform the role.

• 8+ years of hands-on RTL design experience with multiple tape-outs; experience in complex IP, subsystems, or SoC blocks.
• Deep proficiency with Verilog and/or SystemVerilog and proven ability to produce synthesizable, timing-clean, low-power RTL at scale.
• Strong working knowledge of standard protocols such as PCIe, DDR, UFS, USB, and AMBA (AXI, AHB, APB).
• Hands-on experience implementing low-power design techniques and capturing power intent (UPF) across multi-voltage domains.
• Solid understanding of logic synthesis, SDC constraint development, static timing analysis (STA), and equivalence checking flows.
• Familiarity with DFT concepts (scan insertion, ATPG, MBIST); direct experience working with DFT teams is a plus.
• Proven ability to own a subsystem from spec to release and collaborate effectively with verification, implementation, and test teams.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related technical field — or equivalent practical experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.