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ASIC Digital Design Senior Manager (USB IP)

Synopsys
May 17, 2026
Full-time
On-site
Sunnyvale, California, United States
$204,000 - $306,000 USD yearly
RTL Design Jobs, Level - Senior

Job Title

ASIC Digital Design Senior Manager (USB IP)

Role Summary

Lead a team of ASIC digital design engineers responsible for USB digital IP architecture, RTL development, and silicon integration. Balance hands-on RTL work and architecture decisions with people management, cross-functional coordination, and delivery of silicon-proven IP.

Experience Level

Senior — management-level role; responsible for technical direction and team execution.

Responsibilities

Primary responsibilities include:

  • Manage and mentor ASIC digital design engineers, including performance management and career development.
  • Own USB digital architecture and RTL design execution while remaining hands‑on at block, subsystem, and IP integration levels.
  • Define micro‑architecture, design specifications, and implementation approaches for high‑performance, power‑efficient, and scalable interface IP.
  • Lead end‑to‑end digital design activities: architecture definition, RTL development, debug, design convergence, and post‑silicon support.
  • Plan and prioritize design work, balancing hands‑on technical involvement with team schedules and resource needs.
  • Drive design quality through rigorous reviews, coding standards, and RTL maintainability practices.
  • Collaborate with verification and validation teams to ensure smooth IP integration and silicon success.
  • Identify and apply AI‑driven design methodologies and automation to improve workflows and productivity.
  • Communicate design status, technical risks, and trade‑offs to senior management and cross‑functional stakeholders.

Requirements

Must-have technical and management qualifications:

  • Proven experience as a team lead or people manager in an ASIC digital design environment.
  • Extensive hands‑on ASIC RTL design experience with direct ownership of complex digital designs.
  • Deep expertise in USB digital design and architecture or similar high‑speed interface protocols.
  • Strong understanding of ASIC design fundamentals, including clocking, resets, low‑power techniques, and design for test.
  • Experience collaborating with verification, validation, and cross‑functional teams to deliver silicon-proven IP.
  • Experience with AI‑driven tools, flows, and methodologies; familiarity with scripting languages (Perl, TCL, Python) is a plus.

Education Requirements

Bachelor’s degree in Electrical Engineering (BSEE) with 12+ years of relevant experience, or Master’s degree (MSEE) with 10+ years of relevant experience. Degrees in related technical fields or equivalent practical experience are acceptable. No specific certifications were listed.


About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

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Date Posted: 2026-05-13