ASIC Digital Design RTL
SynopsysJob Title
ASIC Digital Design RTL
Role Summary
The role involves designing high-performance digital logic and collaborating across teams on high-speed interconnect technology. The mission is to contribute to innovative chiplet systems in a global engineering environment.
Experience Level
Mid-level; specific years of experience not mentioned.
Responsibilities
The key responsibilities include:
- Designing high-performance digital logic for Die to Die IP.
- Collaborating on PHY and controller designs.
- Optimizing IP for performance, power, and area.
- Participating in the full Hard IP design cycle.
- Providing technical guidance to junior engineers.
- Staying current with industry trends.
Requirements
Must-have skills include:
- Expertise in SerDes, DDR/HBM, or UCIe PHY.
- Hard IP design experience.
- Proficiency in SystemVerilog.
- Strong RTL-to-gate design flow knowledge.
- Excellent problem-solving and communication skills.
Education Requirements
Not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
