ASIC Digital Design Principal Engineer

Job Title

ASIC Digital Design Principal Engineer

Role Summary

Principal-level verification engineer responsible for defining and driving verification strategy and execution for PCIe PHY mixed-signal IP. The role partners with digital, analog, firmware, architecture, and validation teams to ensure protocol compliance, interoperability, and product quality.

Experience Level

Senior / Principal level. (No explicit years-of-experience requirement stated.)

Responsibilities

Drive technical verification activities for complex PCIe PHY IPs and ensure delivery of high-quality mixed-signal products.

• Define and execute verification strategy and functional quality objectives for next-generation PCIe PHY IP.
• Develop comprehensive verification plans for block- and subsystem-level mixed-signal designs.
• Architect and implement advanced testbenches and reusable verification environments.
• Verify PCIe PHY features such as LTSSM behavior, PIPE interactions, link initialization/training, power management, equalization, error handling, and compliance scenarios.
• Apply constrained-random, assertion-based, and coverage-driven methodologies; automate debug and analysis flows.
• Analyze failures, perform root-cause investigations, and drive defect closure across design and verification teams.
• Collaborate with design, analog, firmware, architecture, and validation teams to cover cross-functional use cases.
• Mentor engineers, promote verification best practices, and improve team execution and quality.

Requirements

Core technical and interpersonal requirements for the role.

• Extensive experience in mixed-signal ASIC/IP verification, with demonstrated delivery of complex IP products.
• Strong expertise in PCIe and PCIe PHY verification and behavior.
• Deep understanding of high-speed SerDes/PHY architecture and digital control in mixed-signal contexts.
• Hands-on experience with SystemVerilog, UVM, assertions, and coverage-driven verification.
• Proven ability to develop verification plans, build reusable environments, and close coverage for complex IP.
• Strong debugging and problem-solving skills; able to work independently and drive issues to resolution.
• Excellent communication and collaboration skills for working across global, cross-functional teams.
• Proven experience mentoring and leading technical verification activities.
• Nice to have: familiarity with mixed-signal interoperability testing, compliance test flows, and automation/debug tooling.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.