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ASIC Digital Design Principal Engineer

Synopsys
October 20, 2026
Full-time
Remote friendly (Markham, Ontario, Canada)
Canada
$146,000 - $219,000 USD yearly
ASIC Design Jobs, Level - Senior

Job Title

ASIC Digital Design Principal Engineer

Role Summary

Architect and implement digital subsystems for high-speed SerDes IP used in networking and storage products. Work on mixed-signal blocks (Ethernet, PCIe, SATA, USB PHYs) and drive design decisions across RTL, synthesis, CDC, DFT, and low-power implementation.

Collaborate with verification, analog, implementation, and customer teams; mentor junior engineers and reduce tapeout risk through strong design and verification practices.

Experience Level

Level - Senior. Requires significant experience; the role expects 10+ years of hands-on digital ASIC design experience.

Responsibilities

The main responsibilities include:

  • Architect and design digital subsystems for high-speed SerDes IP (Backplane Ethernet, PCIe, SATA, USB 2/3 PHYs).
  • Translate system-level and analog interface specifications into RTL and implementable design constraints.
  • Define and drive CDC, synthesis, DFT insertion, and low-power architecture decisions across mixed-signal blocks.
  • Collaborate with ASIC verification engineers to define testplans, assertions, and coverage; close functional coverage gaps.
  • Perform gate-level simulation, timing and power analysis, and debug mixed-signal boundary failures.
  • Mentor and train junior engineers on RTL quality, synthesis-aware design, and cross-functional collaboration.
  • Work with design groups and customer support to resolve issues and support silicon bring-up.

Requirements

Must-have skills and experience:

  • 10+ years of hands-on digital ASIC design experience in high-speed or mixed-signal environments.
  • Proficiency in Verilog or VHDL for RTL design and gate-level simulation.
  • Deep knowledge of clock domain crossing design, analysis, and verification methodologies.
  • Hands-on experience with synthesis flows, timing closure, and power optimization.
  • Solid knowledge of DFT methodologies, including scan insertion, ATPG, and boundary scan.
  • Experience working with verification teams on testplan creation, coverage closure, and failure analysis.
  • Ability to communicate across analog, verification, and implementation teams and to mentor others.

Nice-to-have:

  • Familiarity with high-speed digital interfaces such as Ethernet, PCIe, SATA, or USB.

Education Requirements

Master's degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.


About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

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Date Posted: 2026-10-04