ASIC Digital Design Engineer (Staff / Senior Staff)
SynopsysJob Title
ASIC Digital Design Engineer (Staff / Senior Staff)
Role Summary
Design and deliver synthesizable RTL for complex protocol IP cores, working with verification and implementation teams to meet timing, area, power, testability, and signoff requirements. The role is on a product engineering team developing semiconductor IP used in customer systems.
Experience Level
Senior — 4–15+ years of digital design and RTL development experience.
Responsibilities
Primary responsibilities include RTL design, verification support, timing closure, CDC/lint signoff readiness, and automation to improve productivity.
- Contribute to architecture and micro-architecture for complex protocol IP cores.
- Design and implement synthesizable RTL in Verilog/SystemVerilog balancing performance, area, power, and testability.
- Perform RTL-level timing analysis and collaborate with implementation teams on STA, timing constraints, and synthesis.
- Support verification activities: test planning, assertion development, functional debug, and coverage closure.
- Drive CDC/RDC/Lint signoff readiness and design-quality closure.
- Apply and evaluate AI-driven design tools and methodologies to improve design quality and automation.
Requirements
Must-have skills and experience.
- 4–15+ years of experience in digital design and RTL development.
- Hands-on experience implementing synthesizable RTL in Verilog/SystemVerilog.
- Experience with test planning, assertion development, basic verification, functional debug, and coverage closure.
- Practical experience with RTL-level timing analysis, STA, timing constraints, and synthesis.
- Experience with CDC/RDC/Lint-ready design practices and achieving design-quality closure.
- Scripting experience in Python, Tcl, Perl, or shell.
- Strong written and oral communication skills in English and Japanese.
Nice-to-have:
- Direct experience with PCIe or CXL IP design and development.
- Experience with low-power design and power intent using UPF.
- Exposure to UVM, formal verification concepts, or functional safety (ISO 26262, FMEDA).
- Experience mentoring engineers or serving as a technical lead on RTL/IP projects.
- Prior experience in a global product engineering environment.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
