ASIC Digital Design Engineer, Sr. Staff
SynopsysJob Title
ASIC Digital Design Engineer, Sr. Staff
Role Summary
Senior ASIC Digital Design Engineer based in Hyderabad working within the ASIC Digital Design team. Responsible for leading RTL and microarchitecture work for digital ASIC blocks and coordinating with verification, physical design, and system teams.
Experience Level
Senior - typically 7+ years of relevant ASIC digital design experience.
Responsibilities
Typical responsibilities include:
- Lead RTL and microarchitecture design for ASIC digital blocks.
- Develop and review synthesizable Verilog/SystemVerilog code.
- Drive timing, area, and power optimization in collaboration with physical design.
- Work with verification engineers to define test plans and resolve functional issues.
- Perform design reviews and mentor junior engineers.
- Coordinate cross-functional integration with SoC teams and system architects.
Requirements
Must-have:
- Proven experience in ASIC digital design and RTL (Verilog/SystemVerilog).
- Experience with synthesis, timing closure, and static timing analysis flows.
- Strong problem-solving and communication skills for cross-team collaboration.
- Experience leading design efforts or technical mentorship.
Nice-to-have:
- Experience with industry-standard EDA tools and SoC integration.
- Familiarity with low-power design techniques and scripting (Tcl/Python).
Education Requirements
Not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
