ASIC Digital Design DFT Scan
SynopsysJob Title
ASIC Digital Design DFT Scan
Role Summary
The role involves architecting and implementing DFT/scan solutions for ASICs, while collaborating with cross-functional teams to ensure quality and reliability in silicon products.
Experience Level
Mid-level with extensive experience in ASIC digital design and DFT methodologies.
Responsibilities
Key responsibilities include:
- Architecting and implementing DFT/scan solutions for ASICs.
- Defining and executing test strategies with cross-functional teams.
- Integrating scan insertion and ATPG flows.
- Mentoring engineers in DFT best practices.
- Optimizing RTL for scan readiness.
- Collaborating with manufacturing partners to improve yield.
Requirements
Required qualifications include:
- Expertise in ASIC digital design and RTL coding.
- Strong background in DFT/scan architecture and ATPG.
- Experience with scan tools (e.g., Synopsys, Mentor, Cadence).
- Knowledge of silicon manufacturing and yield optimization.
- Leadership and mentoring abilities.
Education Requirements
Information not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
